Fully funded PhD position – University of Leeds and Arm Ltd

Job title:

Fully funded PhD position – University of Leeds and Arm Ltd

Company

University of Leeds

Job description

Job Information Organisation/Company

University of Leeds Research Field

Computer science » Computer architecture Researcher Profile

First Stage Researcher (R1) Country

United Kingdom Application Deadline

3 Apr 2024 – 00:00 (UTC) Type of Contract

To be defined Job Status

Negotiable Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

Identifying and Optimising Worst-Case Latency Bounds in On-Chip Network Interconnects

On-chip interconnects have played a key role in the performance and scalability of multi-core and many-core processors over the past two decades. As those processors are deployed more and more often in time-sensitive and safety-critical applications such as automotive, aerospace and medical systems, it is becoming more important to ensure that their performance is good enough to satisfy all requirements even in worst-case scenarios.

This project will build on recent developments in response-time analysis and network calculus, which are the main real-time analysis methods to identify worst-case latency in on-chip networks. Research work will include a systematic comparison of both methods regarding tightness, complexity/performance and resilience to corner case scenarios, with specific focus on recently discovered effects such as downstream indirect interference and multi-point blocking, which have shown that many state-of-the-art methods are unsafe. The expected outcome will be a methodology for the joint application of both analysis methods, aiming to support the exploration of design alternatives that are predictable (bounded worst-case latency) and efficient (worst-case closer to the average case), and to pave the way towards the inclusion of such analyses into commercial timing analysis tools.

Full description
On-chip interconnects have played a key role in the performance and scalability of multi-core and many-core processors over the past two decades. As those processors are deployed more and more often in time-sensitive and safety-critical applications such as automotive, aerospace and medical systems, it is becoming more important to ensure that their performance is good enough to satisfy all requirements even in worst-case scenarios.

This project will build on recent developments in response-time analysis [1,2] and network calculus [3], which are the main real-time analysis methods to identify worst-case latency in on-chip networks. Research work will include a systematic comparison of both methods regarding tightness, complexity/performance and resilience to corner case scenarios, with specific focus on recently discovered effects such as downstream indirect interference and multi-point blocking, which have shown that many state-of-the-art methods are unsafe [4]. The expected outcome will be a methodology for the joint application of both analysis methods, aiming to support the exploration of design alternatives that are predictable (bounded worst-case latency) and efficient (worst-case closer to the average case), and to pave the way towards the inclusion of such analyses into commercial timing analysis tools.

[1] B. Nikolic, S. Tobuschat, R. Ernst, L. Soares Indrusiak, A. Burns. Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays. Real-Time Syst 55, 63-105 (2019).

[2] L. Soares Indrusiak and A. Burns. Real-Time Guarantees in Routerless Networks-on-Chip. ACM Trans. Embed. Comput. Syst. 22, 5, Article 88 (2023).

[3] R. Zippo and G. Stea. Computationally Efficient Worst-Case Analysis of Flow-Controlled Networks With Network Calculus. IEEE Trans. Inf. Theory 69, 4, 2664-2690 (2023).

[4] L. Soares Indrusiak, A. Burns and B. Nikolic, “Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs,” 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2018, pp. 219-224.

Requirements

Additional Information

Website for additional job details

Work Location(s)

Number of offers available 1 Company/Institute University of Leeds Country United Kingdom City Leeds Geofield

Where to apply Website

Contact City

Leeds Website

STATUS: EXPIRED

Expected salary

Location

Leeds

Job date

Thu, 07 Mar 2024 08:54:27 GMT

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